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Solar Technology and Photovoltaic Cells

Concentrating photovoltaic's (CPV) uses lenses and mirrors to focus the sun's energy. This technology includes both a low-concentration approach, which increases the sun's magnification by between 2 and 100 times, and a high concentration approach, which can increase the magnification by hundreds of suns when the PV efficiency exceeds 40%. CPV uses less photovoltaic material and increases performance, hopefully enough to offset any additional costs.

Concentrating Photovoltaics and Thermal (CPVT) is another technology; this produces both electricity and thermal heat in the same module. Thermal energy itself is a benefit from the sun, and other plants have a design of a solar power tower in which the mirrors focus sunlight on a heat receiver at the top that collects the heat and transfers it to piping inside the tower where is it circulated and used to make electricity. The design minimizes the field of piping to the vertical tower height to a few hundred meters and can reach temperatures in excess of 1000 degrees.While currently there are very few commercially operating tower installations, based on announcements, this technology may grow rapidly.

The Solar Two tower in California is an example of this technology and has the capability to produce 10 megawatts of power. Because of its success, Solar Tres is being built in Spain; this will be three times larger than the Solar Two plant and have a capacity of 17 megawatts. As it is, Solar Two's tower has been removed in 2009 to make way for a larger solar project. Another solar thermal technology is the parabolic trough. The SEGS plants in California utilize this technology and have a capacity of 33 megawatts each. Nevada Solar One is another very large CSP project with a capacity of 64 megawatts, using Flabeg AG troughs made in Germany.

When we look into photovoltaic cell technology and the materials used, throughout the world crystalline silicon has been used as the light-absorbing semiconductor in most solar cells, even though it is a relatively poor absorber of light and requires a considerable thickness of material. Nevertheless, it has proved convenient because it yields stable solar cells with good efficiencies. There are two types of crystalline silicon are used in the industry. The first is mono crystalline, produced by slicing wafers from a high-purity single crystal. The second is multi crystalline silicon, made by sawing a cast block of silicon first into bars and then wafers. Most efficient production cells use mono crystalline c-Si with laser grooved, buried grid contacts for maximum light absorption and current collection. The main trend in crystalline silicon cell manufacture is toward multicrystalline technology. And for both mono- and multicrystalline Si, a semiconductor homo junction is formed by diffusing phosphorus into the top surface of the boron doped (p-type) Si wafer. Screen-printed contacts are applied to the front and rear of the cell, with the front contact pattern specially designed to allow maximum light exposure of the Si material with minimum electrical (resistive) losses in the cell. Crystalline silicon cell technology forms about 90% of solar cell demand. The balance comes from thin film technologies. Approximately 45% of the cost of a silicon cell solar module is driven by the cost of the silicon wafer, a further 35% is driven by the materials required to assemble the solar module.

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Microelectronics Industry and Growth

The remarkable success of information and telecommunication technology within the last few decades has been facilitated by the phenomenal growth of the microelectronics technology. While nanotechnology has future prospects, microelectronics has already transformed global competition and commerce. It offers strategic advantages to firms, institutions and nations through its capacity to develop products and services cheaply and efficiently. It is the engine that drives present global commerce and industry.

The world has experienced many new dimensions in knowledge acquisition, creation, dissemination and usage courtesy of this technology. The advancement of Internet and digital photography could all be linked to better performance from microchips. When microelectronics technology advances, a dawn emerges in global economy in speed, efficiency and capacity.

Microelectronics is considered a very revolutionary technology noting the disruptions it has brought to the dynamics of the global economy via its different applications since its invention by Jack Kilby in the late 1950s. Of the gross world product (GWP), estimated (2007) at about $55 trillion (currency) (The Economist, 2008), microelectronics contributes more than 10%. Microelectronics is very pivotal to many emerging industries in the 21st century with a central position in the global economy. Because Internet, medicine, entertainment and many other industries cannot substantially advance without this technology, it has a vantage position in engineering education in many developed nations.

These nations invest heavily in microelectronics education as in the United States, Canada and Western Europe where the MOSIS, CMC and Europractice programs respectively enable students to fabricate and test their integrated circuits for full cycle design and learning experience on integrated circuits. On the other hand, developing nations increasingly lag behind in adopting and diffusing this technology in their economies owing to many factors, which include human capital and infrastructure. Absence of quality technical education has contributed to stall the transfer, diffusion and development of microelectronics in both the emerging and developing economies.

Microelectronics is a group of technologies that integrate multiple devices into a small physical area. The dimension is about 1000 larger than nanotechnology dimension; micrometer vs. nanometer. Usually, these devices are made from semiconductors like silicon and germanium using lithography, a process that involves the transfer of design patterns unto a silicon wafer. There are accompanying processes which include etching, oxidation, diffusion, etc. Several components are available in microelectronic scale such as transistors, capacitors, inductors, resistors, diodes, insulators and conductors.

The microelectronics can be divided to its subfields which in turn are connected to other micro related fields. These subfields are micro electromechanical systems (MEMS), nanoelectronics, optoelectronics and single electron devices. Integrated circuits or microchips are typical microelectronic devices, which can be found in computers, mobile phones, medical devices, toys and automobiles. There is a high level of convergence between nanotechnology and microelectronics. The major difference lies in the size of the materials; nonetheless, the techniques are very different.

Complementary metal oxide semiconductor (CMOS) transistor is the most common transistor used in the industry owing to its ease of integration and low static power dissipation. Bipolar junction transistor is another popular version. With the sizes of CMOS transistor in the nanometer range, the behaviors of the transistors are radically affected by parasitic noise and power dissipation. These problems pose potential challenges to the continuous progress of CMOS technology and microelectronics industry in general.

The survivability of Moore's Law, (after Gordon Moore, co-founder of Intel Corp) which states that the numbers of transistors in a semiconductor die double every 18 to 24 months, is presently challenged if engineers cannot downscale the transistor size any further efficiently. This scaling has been the driver that has enabled microelectronics products to improve in speed, capacity and cost-efficiency. Many efforts have been geared to overcome the problems faced in the industry as transistors scale into the deep nanometer. They include improving the structure of the metals and polysilicon materials used in making the devices, more enhanced doping profile, new materials to keep the industry alive and well into the future.

Dr. Ndubuisi Ekekwe blogs at Nkpuhe
http://goafrit.wordpress.com

Get Thin Film Solar Panels

Have you ever heard of thin film solar panels? If you are a solar energy system aficionado, you must have read about these great breakthroughs. If not, then this article will give you an idea of what they are and how amazing they can be.

Thin film solar panels, also called as "thin film photovoltaic (PV) solar panels" are a new innovation which has a potential in making solar energy system more affordable. They use the same photovoltaic process that conventional solar panels do. Their PV cells have semiconductors where the sunlight interacts. Once interaction is made, electric current is produced. This energy may be used real-time or may be stored in batteries for later utilization.

So, if they work just like the conventional solar systems, what's new about them?

Well, the difference is obvious: they are thin. The conventional solar panels use crystalline silicon as semiconductor materials. They produce electricity from the sunlight but they are labor-intensive to create. You see, every single cell has to be produced on a solo silicon wafer. This is what makes the panels very expensive. As you know, this is also the reason why they are not widely used. After all, not everyone has the buying capacity.

This is where thin film solar panels come into scene. They use semiconductors which are thinner than crystalline silicon. They can be mass-produced by the use of cheaper materials and automated systems. The process is almost three times less laborious than creating conventional crystalline silicon and this is what makes them a more affordable choice. For entrepreneurs who wish to get into the solar panel marketing business, the start-up capital would be lower. The more entrepreneurs venture into this business, the better for the consumers. Why? Because the lower the prices of solar panels would be!

You know what's another great thing about this thin film technology? It has made the solar cells a lot more compact and lightweight, so much so that they can sometimes be hardly recognizable. They have also become so flexible that you will not have to set up an elaborate structure just to hold your panels in place. These days, you can integrate the thin film into your wall or roof and people wouldn't even notice it's there. Thin film solar panels for metal roofing are already available in the market as well as thin film composition for roof shingles.

Presently, more portable solar energy systems are being produced to power up basic electronic devices used in daily life such as mobile phones, MP3 players, and GPS devices. Laptops and TVs can also now be run by thin film solar technology. These miniature solar panels are compact and lightweight that you can install them in your backpack or slip into your purse. Who would have thought solar power can be this handy? Although they may still cost a lot these days, it won't surely take long before they become affordable to every average Joe (and Jane) who wishes to experience the revolution.

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Semiconductor Parameter Analyzers For Three Critical Types of Semiconductor Measurement - Part III

One of the greatest challenges associated with integrating DC I-V, capacitance-voltage (C-V), and ultra-fast I-V measurement capabilities into a single parametric test chassis is that the cabling required for each measurement type is fundamentally different. Although the cabling from the instrument to the semiconductor probe station bulkhead and feed-through is fairly straightforward, the cabling from the bulkhead to the probe tips can be confusing and difficult.

Different Cabling for Different Measurements. DC I-V measurements are made using four triaxial cables. Guarding is necessary to achieve low current I-V measurements, which makes the use of triaxial cables necessary for these measurements. The measurement signal is carried on the center conductor of the cable, the inner shield is driven as a guard for the signal, and the outer shield is used for safety to shield the user from high voltages that may be applied to the guard and signal conductors. Four cables are necessary in order to achieve a remote sense, or Kelvin, connection to allow the instrument to sense the voltage at the device accurately.

Guarding is a technique that reduces leakage errors and decreases measurement response time. Guarding consists of a conductor (shield) surrounding the lead of a high impedance signal and driven by a low impedance source. The guard voltage is kept at or near the potential of the signal voltage.

C-V measurements are made using four coaxial cables. The outer shells are connected together to control the characteristic impedance the signals see. All four cables' outer shells must be inter-connected near the DUT. Typical cabling requirements for different types of measurements are listed below.

DC I-V Measurements

? Triaxial cables

? Kelvin connections

? Isolated, driven grounds

LCR/C-V Measurements

? Coaxial cables

? Kelvin connections

? Shields connected at the probe tips

Ultra-fast I-V Measurements

? Coaxial cables

? Non-Kelvin connections

? Shields connected at the probe tips

? Shields optionally connected to a probe tip

Ultra-fast I-V measurements require the highest bandwidth of the three measurement types, so the cable must have characteristic impedance that matches the source impedance to prevent reflections off the DUT from reflecting off the source. Ultrafast I-V testing does not use a remote sense cable and is the only one of the three measurement types that connects the DUT to the outer shield of the cable.

To address the challenges created by different cabling requirements for different measurement types; a high-performance multi-measurement cabling system. These cables support I-V, C-V and ultra-fast I-V measurements. Their use reduces the burden on a test system operator, who would otherwise be forced to go through the laborious process of re-cabling connections from the instrumentation to the prober every time a new measurement type is required.

A good cabling kit maximizes signal fidelity by eliminating measurement errors that often result from poor cabling practices. When combined with a versatile parameter analyzer system, the user will be able to make the three principal types of measurement required for semiconductor devices. High-performance multi-measurement cabling is crucial for connecting various elements of a parameter analyzer to the probe manipulators on a wafer prober, especially when you need to integrate accurate ultra-fast I-V, C-V, and precision DC I-V measurements for a high throughput test system

Conclusions

Ultra-fast I-V sourcing and measurement are the latest capabilities to be added to integrated parameter analyzer systems. Modular architectures in these systems represent a cost-effective way to address new testing needs and techniques as they emerge. Multi-measurement cabling with a broad signal bandwidth is crucial for high measurement accuracy and throughput in these systems. Getting all these features and capabilities in one test system that adapts readily to the industry's changing test needs makes a semiconductor manufacturer's capital investment stretch further and improves its ROI.

Lee Stauffer is a Senior Marketer with Keithley Instruments in Cleveland, Ohio, USA, where he is responsible for developing and supporting products for the semiconductor manufacturing and research markets. His formal education in electrical engineering and semiconductor device physics is complemented by more than 20 years experience in semiconductor process and product engineering, device characterization and instrumentation design. He can be reached at 440-248-0400, or by e-mail at lstauffer@keithley.com.

Epitaxy on Silicon-On-Insulator Technology

Introduction:

As at current, we see that CMOS technology is the driving technology of the microelectronics industry, and the conventional way of fabricating integrated circuits on bulk silicon substrates has illustrated problems such as unwanted parasitic effects, latchup, and the difficulty of making shallow junctions. In the recent years, the advent of Silicon-on-Insulator has proven superior in many aspects to their bulk counterparts, and the benefits include the absence of latch-up, the reduced parasitic source and drain capacitances, the ease of making shallow junctions, radiation hardness, ability to operate at high temperature, improved transconductance and sharper subthreshold slope. There are several approaches available to create SOI wafers, and we discuss two particular techniques over here. First, we seek to illustrate a heteroepitaxy technique through the Ultra-Thin Silicon (UTSi) process where high quality Silicon-on-Sapphire (SOS) material is formed. Next, we look at a homoepitaxy technique called Epitaxial Lateral Overgrowth (ELO) technique which seeks to grow a homogenous crystal laterally on an insulator.

Ultra-Thin Silicon (UTSi) Process

Silicon-on-Sapphire (SOS) material was first introduced in 1964. SOS was recognized for its high speed and low power potential. The usage of Czochralski growth of sapphire crystals and the subsequent deposition of a silicon film in an epitaxial reactor had proved inefficient as there was high defect density due to lattice mismatch with defect densities near the Si-Sapphire interface reaching up to planar faults /cm and line defects/cm. This resulted in low resistivity, mobility, and lifetime near the interface. The silicon film deposited is also under compressive stress at room temperature due to different thermal expansion coefficients which may possibly result in relaxation in the film through crystallographic defects such as microtwins, stacking faults, and dislocations. Such consequences are undesired.

Hence, these reasons advocate the need for better heteroepitaxy technique, and in which the UTSi process is one such potential candidate. The steps involved in a UTSi process are as follows: See Figure 1.

Step 1: Grow a relatively thick film of silicon on sapphire. Silane (SiH4) is commonly used as the source of silicon for SOS growth. Its pyrolysis reaction in a carrier hydrogen gas, SiH4 --> Si + 2H2, results in the deposition of a silicon layer over the sapphire substrate. The deposition temperature is usually kept below 1050 deg C in order to prevent the autodeposition of aluminum from the sapphire substrate to the silicon layer. The desired silicon orientation is , which has been achieved on various sapphire orientations, i.e., , , .

Step 2: Implantation of Si into the silicon film is carried out to amorphize the bottom 2/3 of the silicon film, with the exception of a thin superficial layer, where the original defect density is the lowest.

Step 3: A low temperature thermal annealing step is then used to induce solid-phase regrowth of the amorphized silicon, using the top silicon layer as a seed.

Step 4: The silicon film is then thinned to the desired thickness by thermal oxidation, and the subsequent HF strip of the SiO. What remains is the final product of Silicon-on-Sapphire (SOS).

It has been demonstrated that UTSi process is capable of delivering relatively defect-free and stress free SOS material in which devices with a high effective mobility can be made.

One application of the UTSi process is seen in UTSi CMOS transistors. As seen from Figure 2, the fabrication process is much simpler since the deep implants and guard regions are unnecessary thanks to the insulating sapphire substrate, and undesired effects such as leakage currents, latchup, and the RF parasitics are eliminated since the devices now sit on an insulating layer. The performance of the CMOS process is enhanced by as much as two generations of process geometry reduction. The advantages of forming CMOS transistors in the ultra thin silicon layer over insulating sapphire include the following:

* Elimination of substrate capacitance, which allows higher speed at lower power and avoids voltage dependent capacitance distortions

* Fully depleted operation, improving linearity, speed, and low voltage performance

* Excellent isolation which allows integration of multiple RF functions without crosstalk

UTSi circuits are produced that compete in the rapidly expanding wireless and fiber optic markets at higher frequencies and data rates with lower power consumption than standard bulk CMOS, SiGe and GaAs circuits, while still using standard CMOS equipment and processing.

Epitaxial Lateral Overgrowth (ELO) Technique

This technique allows the homoepitaxial growth of silicon on silicon, with the focus placed on growing the crystal laterally on the insulator. In ELO, we can perform this in an atmospheric or in a reduced-pressure epitaxial reactor. The technique consists of the epitaxial growth of silicon from seeding windows over SiO islands or devices capped with an insulator.

The steps involved in a ELO technique are as follows: See Figure 3.

Step 1: An oxide layer is grown on the (100) silicon wafer. Next, patterning is carried out on the oxide to demarcate the windows. The edges of the windows are oriented along the direction.

Step 2: Cleaning of the wafer is carried out

Step 3: Wafer is loaded into an epitaxial reactor and submitted to a high-temperature hydrogen bake to remove the native oxide from the seeding windows.

Step 4: Epitaxial growth is performed next, using e.g: SiHCl +H+ HCL gas mixture.

Step 5: Apply an in-situ HCl etch step to remove any crystallites that may be formed on the oxide due to nucleation of small silicon crystals with random orientation during the epitaxial growth.

Step 6: Once the small nuclei are removed, a new epitaxial growth step is performed, followed by an etch step, and this repeats until the oxide is covered by epitaxial silicon.

Some points we should note is that the epitaxial growth proceeds from the seeding windows both vertically and laterally, and the silicon crystal is limited by the and facets. When two growth fronts, seeded from opposite sides of the oxide, join together, a continuous silicon-on-insulator film is formed, which contains a low-angle subgrain boundary where the two growth fronts meet. A groove is observed over the centre of the SOI area. When more growth is done, this groove disappears.

As much as this is a simple technique to have homoepitaxial growth, a major disadvantage is the nearly 1:1 lateral-to-vertical growth ratio. On the other hand, the thick ELO film allows the design engineer to obtain SOI films of different thickness easily simply by polishing the wafers to required depths as needed. Also, the low defect density and low thermal budget needed to implement a ELO-SOI is considered superior to other technologies such as SIMOX (Separation by Implanted Oxygen) or other SOI processes for submicron devices.

Applications for this technique have been seen in three-dimensional and double-gate devices.

Variations in ELO technique has been witnessed in "tunnel epitaxy", "confined lateral selective epitaxy" (CLSEG) or "pattern-constrained epitaxy" (PACE) whereby a "tunnel" of SiO is created, forcing the epitaxial silicon to propagate laterally instead of vertically. In effect, a 7:1 lateral-to-vertical growth ratio has been obtained, which is more efficient than the original approach.

Jean-Pierre Colinge, Silicon-On-Insulator, Kluwer Academic Publishers, London, 2004.

Originally Written Article here.

The author Jimmy Lee is involved in article writing, publishing, and website design on a freelance basis amid a daytime job as an electrical engineer. His favourite works can be found at http://flashgor.blogspot.com/ and [http://www.diypc.wordpress.com/]